1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a synchronous type semiconductor memory device of a double data rate.
2. Description of the Related Art
Conventional, a memory apparatus like 128-M DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access the memory) is known. FIGS. 1A and 1B are block diagrams showing the outline circuit structure of the memory apparatus. Referring to FIGS. 1A and 1B, the memory device is comprised of a clock signal generating section 120, a memory cell array 1102-1, a memory cell array 2102-2, a data amplifier 1106-1, a data amplifier 2106-2 and an output circuit 108. The clock signal generating section 120 generates internal clock signals ICLK1 and ICLK2 from an external clock signal ECLK and a signal ECLKB as an inversion signal of the signal ECLK. A column decoder (not shown) to specify a Y address and a sense amplifier (not shown) to detect data read from a memory cell are provided in each of the memory cell array 1102-1 and the memory cell array 2102-2. The output circuit 108 has a multiplexer (MUX) 110 and an output latch buffer 114.
Data is read out from the memory cell array 1102-1, is amplified by the data amplifier 106-1 and is outputted on a data bus 10L. Also, data is read from the memory cell array 2102-2, is amplified by the data amplifier 106-2 and is outputted on a data bus 20L. If the data on the data bus 10L is an odd number side, the data on the data bus 20L is an even number side, and if the data on the data bus 10L is the even number side, the data on the data bus 20L is the odd number side.
The multiplexer (MUX) 110 of the output circuit 108 outputs the data on the data buses 10L and 20L to the output latch buffer 114 via a data bus Mout in order in response to the two internal clock signals ICLK1 and ICLK2 which are supplied from the clock signal generating section 120. The output latch buffer 114 outputs the data from the multiplexer (MUX) 110 to an output terminal Dout in order in response to the external clock signals ECLK and ECLKB. In this way, the data of the odd number side and the data of the even number side are outputted during one period of the external clock signal.
FIGS. 2A to 2H are timing charts showing an operation of the conventional memory device shown in FIGS. 1A and 1B. As shown in FIGS. 2A and 2B, the external clock signals ECLK and ECLKB are supplied to the clock signal generating section 120. As shown in FIGS. 2C and 2D, the clock signal generating section 120 generates the internal clock signals ICLK1 and ICLK2 from these external clock signals ECLK and ECLKB. That is, the internal clock signals ICLK1 and ICLK2 are generated to synchronize with the rising edge or falling edge of the external clock signals ECLK or ECLKB, respectively. In this way, the internal clock signals ICLK1 and ICLK2 have the frequency the same as the external clock signal. The internal clock signals ICLK1 and ICLK2 have approximately the same phase as the external clock signals ECLK and ECLKB.
The data DATA1 of the odd number side and data DATA2 of the even number side read out from the memory cell array 1102-1 and the memory cell array 2102-2 are amplified by the data amplifiers 106-1 and 106-2 and are outputted on the data buses 10L and 20L during one period of the internal clock signal, respectively, as shown in FIGS. 2E and 2F.
The above internal clock signals ICLK1 and ICLK2 are supplied to the multiplexer (MUX) 110. As shown in FIG. 2G, the multiplexer (MUX) 110 selects the data DATA1 on the data bus 10L in response to the rising edge of internal clock ICLK1 and outputs it to the output bus Mout. Next, the multiplexer 110 selects the data DATA2 on the data bus 20L in response to the rising edge of the internal clock ICLK2 (the falling edge of the internal clock ICLK1) and outputs it to the output bus Mout. As shown in FIG. 2H, the output latch buffer 114 outputs the data DATA1 and DATA2 from the output terminal Dout in response to the external clock signals ECLK and ECLKB, respectively. In this way, the two data DATA1 and DATA2 can be read out during one period of the external clock signal.
In such a DDR-SDRAM, a layout is often used in which a plurality of memory cell arrays are arranged on both sides of a chip, and a single clock signal generating section 120 is arranged on the center of the chip. The output circuit 108 containing the multiplexer 110 is provided for each memory cell array. The two internal clock signals ICLK1 and ICLK2 generated by the clock signal generating section 120 are supplied to each output circuit 108 as a pair, as shown in FIG. 3.
In 256-MB DDR-SDRAM, a clock signal of 166 MHz is used as the external clock signal, whose one cycle is about 6 ns. In this case, one read cycle is about 3 ns. When a high frequency clock signal is used in this way, there is a case where data cannot be read out right due to the difference between the propagation delay times of the internal clock signal, when the wiring lines for the internal clock signals are different in the length from the clock signal generating section 120 to each output circuit 108. For this reason, the wiring line of the internal clock signal is generally designed for the wiring lengths from the clock signal generating section 120 to the respective output circuits 108 to be equal, for elimination of the difference in the propagation delay time. For this purpose, as shown in FIG. 3, the wiring lines for the two internal clock signals ICLK1 and ICLK2 needs be arranged to be equal in length for the output circuits. However, in the conventional DDR-SDRAM, the mask design becomes complicated and also a chip area is wasted. Especially, when a multiple bit output circuit structure is adopted like the 16-bit output, the arrangement of the clock signal wiring lines becomes very difficult.
Also, as mentioned above, when the internal clock signal is generated using the rising edge or falling edge of the external clock signal, there is no guarantee that the duty ratio of the internal clock signal is 50%. When the duty ratio is not 50%, the durations of the internal clock signals ICLK1 and ICLK2 in the high level are different, and there is a case that the operation margin cannot be secured.
In addition, in a high speed operation DDR-SDRAM, because the period of the read cycle is short, the margin for the setup reduces. Therefore, it is desirable that the internal clock signal used for the reading operation is supplied before the reading cycle. Contrary, when the internal clock signal is too early supplied, the internal clock signal is supplied before the previous cycle ends so that there is possibly erroneous operation.
In conjunction with the above description, a clock system of a semiconductor memory device which uses a frequency multiplier is disclosed in U.S. Pat. No. 6,157,238. In this reference, an external clock signal source generates external clock signals. A controller has a master frequency amplifier and a master DLL circuit. Each of a plurality of DRAMs has the frequency multiplier and the DLL circuit. The frequency multiplier generates an internal clock signal, which has twice of the frequency of the external clock signal, from the external clock signal. The frequency multiplier has a delay circuit, a logical device and a buffer. The delay circuit generates a phase delayed clock signal based on the external clock signal. The logical device generates the internal clock signal based on the external clock signal and the phase delayed clock signal. The buffer buffers the internal clock signal and supplies it.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-298983A). In this reference, the semiconductor memory device has first and second memory sections and an output section. The first memory section stores or outputs data in the rising edge of the clock signal, and the second memory section stores and outputs data in the falling edge of the clock signal. The output section outputs the data from the first and second memory sections in response to the rising edge and falling edge of the clock signal. One of the first and second memory sections, which outputs data first, is arranged near the output section.
Also, a clock multiplying circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-163689). In this reference, a delay circuit has a plurality of delay elements and generates a multi-phase clock signal from the clock signal with an optional duty ratio. A period sensing section detects the number of delay elements necessary to delay the input clock signal for one period. A selecting section outputs a selection signal from the delayed clock signal based on the detected number of delay elements. The multiple clock generating section generates a clock signal with the duty ratio of 50% from the input clock signal through the logic inversion in the rising edge of the selection signal.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-66854). In this reference, each of a plurality of first delay circuits of a delay circuit sequence has first to fourth nodes. The third node is connected to the first node of the adjacent delay circuit, and the fourth node is connected to the second node of the adjacent delay circuit. When the first node is connected to the first power supply during a first period while a first control signal is connected to a first power supply, the second to fourth nodes are connected to a second power supply, the first power supply and the second power supply in order, respectively. Also, when the fourth node is connected to the first power supply during a second period while the first control signal is connected to the second power supply, the third, second and first nodes are connected to the second power supply, the first power supply and the second power supply in order, respectively. Thus, an internal clock signal is generated with no phase difference from an external clock signal.
Therefore, an object of the present invention is to provide a semiconductor memory device in which a single clock signal is supplied to each of output circuits provided for memory cell arrays.
Another object of the present invention is to provide a semiconductor memory device in which an operation margin can be taken widely.
Still another object of the present invention is to provide a semiconductor memory device in which a chip area can be used effectively.
Yet sill another object of the present invention is to provide a semiconductor memory device in which four data can be read out a double data rate.
Also, it is an object of the present invention to provide a semiconductor memory device in which an internal clock signal is generated from external clock signals to have twice of the frequency of the external clock signal and to have the duty ratio of 50%.
In an aspect of the present invention, a semiconductor memory device includes two memory cell array sections, a single clock signal line, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal based on a second clock signal externally supplied and outputs the first clock signal onto the clock signal line. The first clock signal has twice of a frequency of the second clock signal. The multiplexer section is connected with the clock signal line and outputs first data and second data respectively read out from the two memory cell array sections in order during one period of the second clock signal in response to the first clock signal on the clock signal line.
It is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the second clock signal.
In another aspect of the present invention, a semiconductor memory device includes a first data bus which transfers first data, a second data bus which transfers second data, a third data bus, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal from a second clock signal, and the first clock signal has twice of a frequency of the second clock signal. The multiplexer section receives the first data and the second data from the first data bus and the second data bus within one period of the second clock signal, respectively, and outputs the first data and the second data to the third data bus in order within the one period of the second clock signal in response to the first clock signal.
The semiconductor memory device may further include a plurality of memory cell arrays, each of the plurality of memory cell arrays may include a first memory cell array section and a second memory cell array section. The multiplexer section is provided for each of the plurality of memory cell arrays. The first data and the second data are respectively read out from the first memory cell array section and the second memory cell array section in one of the plurality of memory cell arrays and are supplied to the multiplexer section corresponding to the one memory cell array through the first data bus and the second data bus. In this case, the clock signal generating section may be provided for the plurality of memory cell arrays, and the clock signal generating section may supply the first clock signal to a plurality of the multiplexer sections in a same delay time. Also, the multiplexer section may include a selecting section and a control clock signal generating section. The selecting section may transfer the first data to the third data bus in response to a control clock signal and then transfers the second data to the third data bus in response to an inversion signal of the control clock signal. The control clock signal generating section may generate the control clock signal during the one period of the second clock signal in response to the first clock signal.
In this case, the selecting section may include a first transfer gate connected with the first data bus and the third data bus to transfer the first data to the third data bus in response to the control clock signal, and a second transfer gate connected with the second data bus and the third data bus to transfer the second data to the third data bus in response to the inversion signal of the control clock signal. Also, the control clock signal generating section may have a D-type flip-flop with a reset terminal. The inversion output terminal of the D-type flip-flop is connected with a data input terminal thereof. The control clock signal is outputted from an inversion output terminal of the D-type flip-flop in response to the first clock signal, and the D-type flip-flop is reset in response to a reset signal supplied to the reset terminal.
Also, it is desirable that two periods of the first clock signal corresponding to the one period of the second clock signal are equal to each other in time length. In addition, it is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the second clock signal. Otherwise, it is desirable that the clock signal generating section generates the first clock signal based on one of a rising edge and a falling edge of the second clock signal.
In still another aspect of the present invention, a semiconductor memory device includes a first data bus which transfers first data, a second data bus which transfers second data, a third data bus which transfers third data, a fourth data bus which transfers fourth data, and a fifth data bus. A clock signal generating section generates a single first clock signal from a second clock signal, and the first clock signal has twice of a frequency of the second clock signal. A multiplexer section receives the first to fourth data from the first to fourth data buses, respectively, outputs the first data and the second data to the fifth data bus in order in a first period of the second clock signal, in response to the first clock signal, and outputs the third data and the fourth data to the fifth data bus in order to a second period of the second clock signal subsequent to the first period.
The semiconductor memory device may further include a plurality of memory cell arrays, each of the plurality of memory cell arrays may include first to fourth memory cell array sections. The multiplexer section is provided for each of the plurality of memory cell arrays. The first to fourth data are read out from the first to fourth memory cell array sections in one of the plurality of memory cell arrays, and are supplied to the multiplexer section corresponding to the one memory cell array through the first to fourth data buses. In this case, the clock signal generating section may be provided for each of the plurality of the memory cell arrays, and the clock signal generating section may supply the first clock signal to a plurality of the multiplexer sections in a same delay time.
Also, the multiplexer section may include a selecting section which transfers the first to fourth data to the fifth data bus in response to first to fourth control clock signals, and a control clock signal generating section which generates the first and second control clock signals during the first period of the second clock signal in response to the first clock signal, and generates the third and fourth control clock signals in the second period of the second clock signal. In this case, the selecting section may include a first transfer gate connected with the first data bus and the fifth data bus to transfer the first data to the fifth data bus in response to the first control clock signal, a second transfer gate connected with the second data bus and the fifth data bus to transfer the second data to the fifth data bus in response to the second control clock signal, a third the transfer gate connected with the third data bus and the fifth data bus to transfer the third data to the fifth data bus in response to the third control clock signal, and a fourth transfer gate connected with the fourth data bus and the fifth data bus to transfer the fourth data to the fifth data bus in response to the fourth control clock signal. Also, the control clock signal generating section has a counter with a reset terminal. The counter counts the first clock signal to output the first to fourth control clock signals, and the counter is reset in response to a reset signal supplied to the reset terminal.
Also, it is desirable that adjacent periods of the first clock signal corresponding to one period of the second clock signal are equal to each other. Moreover, it is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the first clock signal. Otherwise, it is desirable that the clock signal generating section generates the first clock signal based on one of a rising edge and a falling edge of the clock signal.
In yet still another aspect of the present invention, a method of reading out data from a specified one of a plurality of memory cell arrays, may be achieved by (a) generating a single first clock signal from a second clock signal, the first clock signal having N times (N is an integer more than 1) of a frequency of the second clock signal; by (b) transferring the first clock signal to the plurality of memory cell arrays in a same delay time; by (c) generating N control clock signals from the first clock signal; and by (d) outputting N data read out from the specified memory cell array during one period of the second clock signal, in response to the N control clock signals as a series of the N data.
It is desirable that the first clock signal has a phase more progressive by a predetermined phase than the second clock signal.